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DESCRIPTION
The WM8195 is a 14-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset Adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 14-bit analogue-to-digital converter. The digital output data is available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed format, with no missing codes. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. Alternatively an external reference level may be applied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8195 typically only consumes 210mW when operating from a single 5V supply and less than 20A when in power down mode.
WM8195
14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser
FEATURES
* * * * * * * * * * * * * * 14-bit ADC No missing codes guaranteed 12MSPS conversion rate Low power - 210mW typical 5V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 14-bit parallel or 8, 7 or 4-bit wide multiplexed data output formats Internally generated voltage references 48-lead TQFP package Serial or parallel control interface
APPLICATIONS
* * * * Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface
BLOCK DIAGRAM
VRLC/VBIAS VSMP MCLK AVDD1-2 DVDD1-3 VRT VRX VRB
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CL RS VS TIMING CONTROL
R G B M U X 8
WM8195
VREF/BIAS OFFSET DAC + PGA
8
OEB + I/P SIGNAL POLARITY ADJUST M U X 14BIT ADC DATA I/O PORT OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] OP[8] OP[9] OP[10] OP[11] OP[12] OP[13]/SDO
RINP
RLC
M U X
CDS
R G B M U X
GINP
RLC
CDS
8
+ OFFSET DAC
PGA
8
+ I/P SIGNAL POLARITY ADJUST
BINP
RLC
CDS
8
+ OFFSET DAC
PGA
8
+ I/P SIGNAL POLARITY ADJUST CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE SEN/STB SCK/RNW SDI/DNA RLC/ACYC NRESET
RLC DAC
4
AGND1-6
DGND1-5
WOLFSON MICROELECTRONICS plc
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Production Data July 2005 Rev 4.1
Copyright 2005 Wolfson Microelectronics plc.
WM8195 TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7
INPUT VIDEO SAMPLING............................................................................................... 9 OUTPUT DATA TIMING .................................................................................................. 9 SERIAL INTERFACE ..................................................................................................... 11
PARALLEL INTERFACE......................................................................................12
INTRODUCTION ........................................................................................................... 13 INPUT SAMPLING......................................................................................................... 13 RESET LEVEL CLAMPING (RLC) ................................................................................. 13 CDS/NON-CDS PROCESSING ..................................................................................... 14 OFFSET ADJUST AND PROGRAMMABLE GAIN......................................................... 15 ADC INPUT BLACK LEVEL ADJUST ............................................................................ 16 OVERALL SIGNAL FLOW SUMMARY .......................................................................... 16 CALCULATING OUTPUT FOR ANY GIVEN INPUT ...................................................... 17 OUTPUT FORMATS...................................................................................................... 18 CONTROL INTERFACE ................................................................................................ 19 TIMING REQUIREMENTS............................................................................................. 20 PROGRAMMABLE VSMP DETECT CIRCUIT ............................................................... 21 REFERENCES............................................................................................................... 21 POWER SUPPLY .......................................................................................................... 22 POWER MANAGEMENT ............................................................................................... 22 LINE-BY-LINE OPERATION .......................................................................................... 22 OPERATING MODES .................................................................................................... 24 OPERATING MODE TIMING DIAGRAMS ..................................................................... 25
DEVICE CONFIGURATION .................................................................................27
REGISTER MAP ............................................................................................................ 27 REGISTER MAP DESCRIPTION................................................................................... 28
RECOMMENDED EXTERNAL COMPONENTS ..................................................31 PACKAGE DIMENSIONS ....................................................................................32 IMPORTANT NOTICE ..........................................................................................33
ADDRESS:..................................................................................................................... 33
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WM8195
PIN CONFIGURATION
OP[13]/SDO OP[12] OP[11] NRESET NC DGND5 VRB AGND6 AGND5 AVDD2 AVDD1 VRT VRX VRLC/VBIAS AGND1 BINP AGND2 GINP AGND3 RINP AGND4 DVDD1 OEB SEN/STB 1 2 3 4 5 6 7 8 9 10 11
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
DGND4 DVDD3 OP[10] OP[9] OP[8] OP[7] DGND3 OP[6] OP[5] OP[4] OP[3] DGND2
25 12 13 14 15 16 17 18 19 20 21 22 23 24
VSMP RLC/ACYC
SDI/DNA SCK/RNW
MCLK DGND1
ORDERING INFORMATION
DEVICE TEMPERATURE RANGE 0 to 70C PACKAGE 48-lead TQFP 1mm thick body (Pb-free) 48-lead TQFP 1mm thick body (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL2 PEAK SOLDERING TEMPERATURE 260oC
XWM8195SCFT/V
DVDD2
OP[0]
OP[1] OP[2]
NC NC
XWM81955CFT/RV
0 to 70C
MSL2
260oC
Note: Reel quantity = 2,200
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WM8195 PIN DESCRIPTION
PIN 1 2 NAME VRX VRLC/VBIAS TYPE Analogue output Analogue I/O DESCRIPTION Input return bias voltage. This pin must be decoupled to AGND via a capacitor.
Production Data
Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be decoupled to AGND via a capacitor. VRLC can be externally driven if programmed Hi-Z. Analogue ground (0V). Blue channel input video. Analogue ground (0V). Green channel input video. Analogue ground (0V). Red channel input video. Analogue ground (0V). Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when OEB = 1. Serial interface: enable pulse, active high Parallel interface: strobe, active low Latched on NRESET rising edge: if Low then device control is via serial interface, if high then device control is via parallel interface.
3 4 5 6 7 8 9 10 11 12
AGND1 BINP AGND2 GINP AGND3 RINP AGND4 DVDD1 OEB SEN/STB
Supply Analogue input Supply Analogue input Supply Analogue input Supply Supply Digital input Digital input
13 14
SDI/DNA SCK/RNW
Digital input Digital input
Serial interface: serial input data signal Serial interface: serial clock signal
Parallel interface: High = data, Low = address Parallel interface: High: OP[13:6] is output bus. Low: OP[13:6] is input bus (Hi-Z). ACYC autocycles between R, G, B inputs when in Line-by-Line mode.
15 16
VSMP RLC/ACYC
Digital input Digital input
Video sample synchronisation pulse. RLC (active high) selects reset level clamp on a pixel-by-pixel basis - tie high if used on every pixel.
17 18 19 20 21 22 23
MCLK DGND1 NC NC OP[0] OP[1] OP[2]
Digital input Supply
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). No connection. No connection.
Digital output Digital output Digital output
Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes: Hi-Z: when OEB = 1. 14-bit output: 14-bit data is output on OP[13:0]. 8-bit multiplexed output: data is output on OP[13:6] at 2 ADC conversion rate. 7-bit multiplexed output: data is output on OP[13:6] at 2 ADC conversion rate. 4-bit multiplexed output: data is output on OP[13:10] at 4 ADC conversion rate. See Output Formats section in Device Description for further details. Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0, and SEN/STB = 0. Output 8-bit: register read back data is output in parallel on OP[13:6] when SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1. Digital I/O supply (3.3V/5V). Digital ground (0V). See pins 21 to 23 for details.
24 25 26 27 28 29 30
DVDD2 DGND2 OP[3] OP[4] OP[5] OP[6] DGND3
Supply Supply Digital output Digital output Digital output Digital I/O Supply
Digital ground (0V).
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Production Data PIN 31 32 33 34 35 36 37 38 39 NAME OP[7] OP[8] OP[9] OP[10] DVDD3 DGND4 OP[11] OP[12] OP[13]/SDO TYPE Digital I/O Digital I/O Digital I/O Digital I/O Supply Supply Digital I/O Digital I/O Digital I/O Digital I/O supply (3.3V/5V). Digital ground (0V). DESCRIPTION See pins 21 to 23 for details.
WM8195
See pins 21 to 23 for details. If the device has been configured to use the serial interface, pin OP[13]/SDO may be used to output register read-back data when OEB = 0 and SEN has been pulsed high. See Serial Interface sections in Device Description for further details. Digital ground (0V). No connection. Reset input, active low. This signal forces a reset of all internal registers and selects whether the serial or parallel control interface is used. See pin SEN/STB. Analogue supply (5V). Analogue supply (5V). Analogue ground (0V). Analogue ground (0V). Lower reference voltage. This pin must be capacitively decoupled to AGND. Lower reference voltage. This pin must be capacitively decoupled to AGND.
40 41 42 43 44 45 46 47 48
DGND5 NC NRESET AVDD1 AVDD2 AGND5 AGND6 VRB VRT
Supply Digital input Supply Supply Supply Supply Analogue output Analogue output
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WM8195 ABSOLUTE MAXIMUM RATINGS
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Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Analogue supply voltages: AVDD1, 2 Digital supply voltages: DVDD1 - 3 Digital grounds: DGND1 - 5 Analogue grounds: AGND1 - 6 Digital inputs, digital outputs and digital I/O pins Analogue inputs (RINP, GINP, BINP) Other pins Operating temperature range: TA Storage temperature Notes: 1. 2. GND denotes the voltage of any ground pin. AGND1 - 6 and DGND1 - 5 pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V 0C -65C MAX GND + 7V GND + 7V GND + 0.3V GND + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V +70C +150C
RECOMMENDED OPERATING CONDITIONS
CONDITION Operating temperature range Analogue supply voltage Digital core supply voltage Digital I/O supply voltage 5V I/O 3.3V I/O SYMBOL TA AVDD1, 2 DVDD1 DVDD2, 3 DVDD2, 3 MIN 0 4.75 4.75 4.75 2.97 5.0 5.0 5.0 3.3 TYP MAX 70 5.25 5.25 5.25 3.63 UNITS C V V V V
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WM8195
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions) NO MISSING CODES GUARANTEED Conversion rate Full-scale input voltage range (see Note 1) Input signal limits (see Note 2) Full-scale transition error Zero-scale transition error Differential non-linearity Integral non-linearity Channel to channel gain matching Total output noise References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current RLCDAC resolution RLCDAC step size, RLCDAC = 0 RLCDAC step size, RLCDAC = 1 RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLC deviation Offset DAC, Monotonicity Guaranteed Resolution Differential non-linearity Integral non-linearity Step size Output voltage Notes: 1. 2. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. Input signal limits are the limits within which the full-scale input voltage signal must lie. PD Rev 4.1 July 2005 7 Code 00(hex) Code FF(hex) DNL INL 8 0.1 0.25 2.04 -260 +260 0.5 1 bits LSB LSB mV/step mV mV VRLCSTEP VRLCSTEP VRLCBOT VRLCBOT VRLCTOP VRLCTOP -50 VRLC = 0 to AVDD 4 0.25 0.17 0.39 0.26 4.16 2.81 +50 50 5 2 1 mA A bits V/step V/step V V V V mV VRT VRB VRX VRTB 1.4 2.85 1.35 1.65 1.5 1 1.6 V V V V Min Gain Max Gain DNL INL VIN Gain = 0dB; PGA[7:0] = 4B(hex) Gain = 0dB; PGA[7:0] = 4B(hex) Max Gain Min Gain 0 20 20 1.25 8 1 1 3 12 0.4 4.08 AVDD MSPS Vp-p Vp-p V mV mV LSB LSB % LSB rms LSB rms
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WM8195
Production Data
Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER Programmable Gain Amplifier Resolution Gain Max gain, each channel Min gain, each channel Gain error, each channel Analogue to Digital Converter Resolution Speed Full-scale input range (2*(VRT-VRB)) DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current Digital IO Pins Applied high level input voltage Applied low level input voltage High level output voltage Low level output voltage Low level input current High level input current Input capacitance High impedance output current Supply Currents Total supply current - active (Three channel mode) Total supply current - active (Single channel mode) Total analogue supply current - active (Three channel mode) Total analogue supply current - active (One channel mode) Digital core supply current, DVDD1 - active (Note1) Digital I/O supply current, DVDD2 - active (Note1) Supply current - full power down mode IAVDD IAVDD MCLK = 24MHz LINEBYLINE = 1 MCLK = 24MHz MCLK = 24MHz LINEBYLINE = 1 MCLK = 24MHz MCLK = 24MHz MCLK = 24MHz 42 35 37 30 3 2 20 60 65 mA mA mA mA mA mA A VIH VIL VOH VOL IIL IIH CI IOZ 5 1 IOH = 1mA IOL = 1mA DVDD2/3 - 0.5 0.5 1 1 0.8 DVDD2/3 0.2 DVDD2/3 V V V V A A pF A VOH VOL IOZ IOH = 1mA IOL = 1mA DVDD2/3 - 0.5 0.5 1 V V A VIH VIL IIH IIL CI 5 0.8 DVDD2/3 0.2 DVDD2/3 1 1 V V A A pF 14 12 3 bits MSPS V GMAX GMIN 8
208 283 - PGA[7 : 0]
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
bits V/V V/V V/V %
7.4 0.74 1
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WM8195
INPUT VIDEO SAMPLING
tPER MCLK tVSMPSU VSMP INPUT tVSU VIDEO tVH tRSU tRH tVSMPH tMCLKH tMCLKL
Figure 1 Input Video Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER MCLK period MCLK high period MCLK low period VSMP set-up time VSMP hold time Video level set-up time Video level hold time Reset level set-up time Reset level hold time Notes: 1. 2. tVSU and tRSU denote the set-up time required after the input video signal has settled. Parameters are measured at 50% of the rising/falling edge. SYMBOL tPER tMCLKH tMCLKL tVSMPSU tVSMPH tVSU tVH tRSU tRH TEST CONDITIONS MIN 41.6 18.8 18.8 6 3 10 3 10 3 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
OUTPUT DATA TIMING
MCLK tPD
OP[13:0]
Figure 2 Output Data Timing
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WM8195
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OEB tPZE OP[13:0] Hi-Z tPEZ Hi-Z
Figure 3 Output Data Enable Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER Output propagation delay Output enable time Output disable time SYMBOL tPD tPZE tPEZ TEST CONDITIONS IOH = 1mA, IOL = 1mA MIN TYP MAX 40 20 15 UNITS ns ns ns
MCLK tACYCSU RLC/ACYC tACYCH tACYCSU tACYCH
PGA/OFFSET MUX OUTPUT
Figure 4 Auto Cycle Timing Test Conditions AVDD = DVDD1 = 4.75 to 5.25V, DVDD2 = 2.97 to 3.63V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 32MHz unless otherwise stated. PARAMETER Auto Cycle set-up time Auto Cycle hold time SYMBOL tACYCSU tACYCH TEST CONDITIONS MIN 6 3 TYP MAX UNITS ns ns
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WM8195
SERIAL INTERFACE
tSPER SCK tSSU SDI tSCE SEN tSERD ADC DATA SDO MSB REGISTER DATA LSB tSCRD t SCRDZ ADC DATA tSEW tSEC tSH tSCKL tSCKH
Figure 5 Serial Interface Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time SEN pulse width SEN low to SDO = Register data SCK low to SDO = Register data SCK low to SDO = ADC data SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW tSERD tSCRD tSCADC TEST CONDITIONS MIN 41.6 18.8 18.8 6 6 12 12 25 30 30 30 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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WM8195 PARALLEL INTERFACE
tSTB STB tASU OP[13:6] Hi-Z
ADC DATA OUT ADDRESS IN DATA IN
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tAH
tDSU
tDH Hi-Z
tSTDO
ADC DATA OUT
tSTAO
REG. DATA OUT ADC DATA OUT
tADLS DNA tOPZ RNW
tADLH
tADHS
tADHH
tOPD
Figure 6 Parallel Interface Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 24MHz unless otherwise stated. PARAMETER RNW low to OP[13:6] Hi-Z Address set-up time to STB low DNA low set-up time to STB low Strobe low time Address hold time from STB high DNA low hold time from STB high Data set-up time to STB low DNA high set-up time to STB low Data hold time from STB high Data high hold time from STB high RNW high to OP[13:6] output Data output propogation delay from STB low ADC data out propogation delay from STB high SYMBOL tOPZ tASU tADLS tSTB tAH tADLH tDSU tADHS tDH tADHH tOPD tSTDO tSTAO 0 5 30 5 5 0 5 5 5 30 30 30 TEST CONDITIONS MIN TYP MAX 10 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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WM8195
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1. The WM8195 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), a 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 14-bit digital word. The digital output from the ADC is presented on a 14-bit wide bus, with optional 8+6-bit, 7+7-bit or 4+4+4+2-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial or parallel interface.
INPUT SAMPLING
The WM8195 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP GINP BINP RINP...) together with the PGA and offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8195 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8195 side of this capacitor to a suitable voltage during the CCD reset period. A typical input configuration is shown in Figure 7 An internal clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8195 side of CIN, at RINP, is forced to the VRLC/VBIAS voltage (VVRLC) by closing of switch 1. When the CL pulse turns off, switch 1 opens, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/Non-CDS Processing section.
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WM8195
RLC/ACYC MCLK VSMP
Production Data
TIMING CONTROL CL RS VS
FROM CONTROL INTERFACE
CIN
S/H +
RINP 1
RLC
2
+
S/H CDS INPUT SAMPLING BLOCK FOR RED CHANNEL
TO OFFSET DAC
EXTERNAL VRLC VRLC/ VBIAS
4-BIT RLC DAC VRLCEXT
CDS
FROM CONTROL INTERFACE
Figure 7 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected pixel-by-pixel by pin RLC/ACYC. Figure 8 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period. The input signal applied to the RLC/ACYC pin is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 9). If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit RLCINT determines whether clamping is applied.
MCLK
VSMP
ACYC/RLC or RLCINT
1
X Programmable Delay
X
0
X
X
0
CL (CDSREF = 01)
INPUT VIDEO
RGB
RGB RLC on this Pixel
RGB No RLC on this Pixel
Figure 8 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this sets switch 2 into the position shown in (Figure 7) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 9.
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WM8195
MCLK VSMP
VS RS/CL (CDSREF = 00) RS/CL (CDSREF = 01) RS/CL (CDSREF = 10) RS/CL (CDSREF = 11)
Figure 9 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode; non-CDS processing is achieved by setting switch 2 in the lower position. CDS = 0.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0]. The gain characteristic of the WM8195 PGA is shown in Figure 10. Figure 11 shows the maximum device input voltage that can be gained up to match the ADC full-scale input range (3V).
Peak input voltage to match ADC Fullscale Input Range
8 7 6 PGA Gain (V/V) 5 4 3 2 1 0 0 64 128 192 Gain register value (PGA[7:0]) 256
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 64 128 192 Gain register value (PGA[7:0]) 256
Figure 10 PGA Gain Characteristic
Figure 11 Peak Input Voltage to Match ADC Full-scale Range
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (Red Green Blue Red...) by pulsing the ACYC/RLC pin, or controlled via the FME, ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
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WM8195
ADC INPUT BLACK LEVEL ADJUST
Production Data
The output from the PGA should be offset to match the full-scale range of the ADC (3V). For negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11. Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 12 represents the processing of the video signal through the WM8195.
INPUT SAMPLING OFFSET DAC PGA BLOCK BLOCK BLOCK
ADC BLOCK
OUTPUT INVERT BLOCK
V1
VIN CDS = 1 VRESET CDS = 0 VVRLC RLCEXT=1 RLCEXT=0
Offset DAC
V2
++
V3
+
-
X
analog
x (16383/VFS) +0 if PGAFS[1:0]=11 +16383 if PGAFS[1:0]=10 +8191 if PGAFS[1:0]=0x
D1
digital
D2
OP[13:0]
D2 = D1 if INVOP = 0 D2 = 16383-D1 if INVOP = 1 PGA gain A = 208/(283-PGA[7:0]) 260mV*(DAC[7:0]-127.5)/127.5 VIN is RINP or GINP or BINP VRESET is VIN sampled during reset clamp VVRLC is voltage applied to VRLC pin CDS, RLCEXT,RLCV[3:0], DAC[7:0], PGA[7:0], PGAFS[1:0] and INVOP are set by programming internal control registers. CDS = 1 for CDS, 0 for non-CDS
RLC DAC
VRLCSTEP *RLCV[3:0] + VRLCBOT
Figure 12 Overall Signal Flow The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 14-bit unsigned digital output, D1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
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CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals though the WM8199. The values of V1 V2 and V3 are often calculated in reverse order during device setup. The PGA value is written first to set tshe input Voltage range, the Offset DAC is then adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the reset level correctly during operation. Note: Refer to WAN0123 for detailed information on device calibration procedures. The following equations describe the processing of the video and reset level signals through the WM8195.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET ................................................................... Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC .................................................................... Eqn. 2
If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC = (VRLCSTEP RLCV[3:0]) + VRLCBOT ................................. Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the offset DAC output. V2 = V1 + {260mV (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain, V3 = V2 208/(283- PGA[7:0]) .............................................. Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 14-bit unsigned number, with input range configured by PGAFS[1:0]. D1[13:0] = INT{ (V3 /VFS) 16383} + 8191 D1[13:0] = INT{ (V3 /VFS) 16383} PGAFS[1:0] = 00 or 01 ...... PGAFS[1:0] = 11 ............... Eqn. 6 Eqn. 7 Eqn. 8
D1[13:0] = INT{ (V3 /VFS) 16383} + 16383 PGAFS[1:0] = 10 ............... where the ADC full-scale range, VFS = 3V.
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP. D2[13:0] = D1[13:0] D2[13:0] = 16383 - D1[13:0] (INVOP = 0) ...................... (INVOP = 1) ...................... Eqn. 9 Eqn. 10
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OUTPUT FORMATS
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The digital data output from the ADC is available to the user in either 14-bit parallel or 8/7/4-bit wide multiplexed formats by setting control bits MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 13 shows the output data formats for Modes 1 - 2 and 4 - 6. Figure 14 shows the output data formats for Mode 3. Table 1 summarises the output data obtained for each format.
MCLK
MCLK
14-BIT PARALLEL OUTPUT
A
14-BIT PARALLEL OUTPUT
A
8+6 AND 7+7-BIT OUTPUT
A
B
8+6 AND 7+7-BIT OUTPUT
A
B
4+4+4+2-BIT OUTPUT
A
B
C
D
4+4+4+2-BIT OUTPUT
ABABCD
Figure 13 Output Data Formats (Modes 1 - 2, 4 - 6)
Figure 14 Output Data Formats (Mode 3) OUTPUT PINS OP[13:0] OP[13:6] OP[13:6] OP[13:10] OUTPUT A = d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0 A = d13, d12, d11, d10, d9, d8, d7, d6 B = d5, d4, d3, d2, d1, d0, CC, OVRNG A = d13, d12, d11, d10, d9, d8, d7, CC B = d6, d5, d4, d3, d2, d1, d0, OVRNG A = d13, d12, d11, d10 B = d9, d8, d7, d6 C = d5, d4, d3, d2 D = d1, d0, CC, OVRNG
OUTPUT FORMAT 14-bit parallel 8+6-bit multiplexed 7+7-bit 4+4+4+2-bit (nibble)
MUXOP[1:0] 00 01 10 11
Table 1 Details of Output Data Shown in Figure 13 and Figure 14.
FLAGS
The following flags are output during multiplexed modes: CC can be used in colour modes 1 and 5 to identify the green channel output, from which the blue and red data can be identified. INPUT RINP GINP BINP CC 0 1 0
Table 2 Input Sampled Flags CC[1:0] OVRNG indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = out of range, 0 = within range.
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WM8195
CONTROL INTERFACE
The internal control registers are programmable via the serial or parallel digital control interface. The register contents can be read back via the parallel interface on pins OP[13:6], or via the serial interface on pin OP[13]/SDO. Note: It is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. This ensures that all registers are set to their default values (as shown in Table 6).
SERIAL INTERFACE: REGISTER WRITE
Figure 15 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Address SEN
Data Word
Figure 15 Serial Interface Register Write Using the serial interface, a software reset is carried out by writing to Address "000100" with any value of data (i.e. Data Word = XXXXXXXX).
SERIAL INTERFACE: REGISTER READ-BACK
Figure 16 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[13], therefore OEB should always be held low when register read-back data is expected on this pin. The next word may be read in to SDI while the previous word is still being output on SDO.
SCK
SDI
a5 1 a3 a2 a1 a0
x
x
x
x
x
x
x
x
Address SEN SDO/ OP[13] OEB
Data Word
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
Figure 16 Serial Interface Register Read-back
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PARALLEL INTERFACE: REGISTER WRITE
Production Data
Figure 17 shows register write in parallel mode. The parallel interface uses bits OP[13:6] of the output bus and the STB, DNA and RNW pins. Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The 6-bit address (a5, 0, a3, a2, a1, a0) is input into OP[11:6], LSB into OP[6], (OP[12] and OP[13] are ignored) when DNA is low, then the 8-bit data word is input into OP[13:6], LSB into OP[6], when DNA is high. The data bus OP[13:6] for both address and data is clocked in on the falling edge of STB. Note all valid registers have address bit a4 equal to 0.
STB
Driven by AFE Driven Externally Hi-Z Address Data Hi-Z Driven by AFE Normal Output Data
OP[13:6]
Normal Output Data
DNA
RNW
Figure 17 Parallel Interface Register Write Using the parallel interface, a software reset is carried out by writing "000100" to OP[13:8] when RNW and DNA are low. Any value of data can be written for this address when DNA changes to high (i.e. Data = XXXXXXXX on OP[15:8]).
PARALLEL INTERFACE: REGISTER READ-BACK
Figure 18 shows register read-back in parallel mode. Read-back is initiated by writing the 6-bit address (a5, 1, a3, a2, a1, a0) into OP[11:6] by pulsing the STB pin low. Note that a4 = 1 and pins RNW and DNA are low. When RNW and DNA are high and STB is strobed again, the contents (d7, d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on OP[13:6], LSB on pin OP[6]. Until STB is pulsed low, the current contents of the ADC (shown as Normal Output Data) will be present on OP[13:6]. Note that the register data becomes available on the output data pins so OEB should be held low when read-back data is expected.
STB
Driven by AFE Hi-Z Driven Externally Address Hi-Z Read Data Driven by AFE Normal Output Data
OP[13:6]
Normal Output Data
DNA
RNW
Figure 18 Parallel Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock (VSMP) of up to 12MHz are required. These clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 5.
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WM8195
PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8195. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8195 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 19 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
MCLK INPUT PINS VSMP POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP
VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS
Figure 19 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS.
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POWER SUPPLY
Production Data
The WM8195 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered on or off completely by setting the EN bit and SELPD bit low. Alternatively, when control bit SELPD is high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. In Line-by-Line operation, the green and blue channel PGAs are automatically powered down. All the internal registers maintain their previously programmed value in power down modes and the control interface inputs remain active. Table 3 summarises the power down control bit functions. EN 0 1 X SELDPD 0 0 1 Device completely powers down. Device completely powers up. Blocks with respective SELDIS[3:0] bit high are disabled.
Table 3 Power Down Control
LINE-BY-LINE OPERATION
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to accommodate this type of signal the WM8195 can be set into Monochrome mode, with the input channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8195 can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in MONO mode (because only one colour is sampled at a time) through the red channel. Figure 20 shows the signal path when operating in colour line-by-line mode.
VRLC/VBIAS VSMP MCLK
CL
RS VS TIMING CONTROL
R G B 8
OFFSET MUX
OFFSET DAC + PGA
8
RINP
RLC
INPUT MUX
CDS
R G B
+ I/P SIGNAL POLARITY ADJUST
14BIT ADC
DATA I/O PORT
OP[13:0]
GINP
RLC
PGA MUX
BINP
RLC
RLC DAC
4
CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE
SEN/STB SCK/RNW SDI/DNA RLC/ACYC NRESET
Figure 20 Signal Path When in Line-by-Line Mode In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be autocycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit. See Figure 4 for detailed timing information. The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to be reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible.
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WM8195
FME 0 0 1 ACYCNRLC 0 1 0 NAME Internal, no force mux Auto-cycling, no force mux Internal, force mux Auto-cycling, force mux DESCRIPTION Input mux, offset and gain registers determined by internal register bits INTM1, INTM0. Input mux, offset and gain registers auto-cycled, RINP GINP BINP RINP... on RLC/ACYC pulse. Input mux selected from internal register bits FM1, FM0; Offset and gain registers selected from internal register bits INTM1, INTM0. Input mux selected from internal register bits FM1, FM0; Offset and gain registers auto-cycled, RED GREEN BLUE RED... on RLC/ACYC pulse.
1
1
Table 4 Colour Selection Description in Line-by-Line Mode
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OPERATING MODES
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Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE 4MSPS x 3 chans SENSOR INTERFACE DESCRIPTION The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 12MSPS max. As mode 1 except: Only one input channel at a time is continuously sampled. Identical to mode 2 TIMING REQUIREMENTS MCLK max = 24MHz MCLK: VSMP ratio is 6:1 REGISTER CONTENTS WITH CDS SetReg1: 03(hex) REGISTER CONTENTS WITHOUT CDS SetReg1: 01(hex)
1
Colour Pixel-by-Pixel
Yes
2
Monochrome/ Colour Line-by-Line
Yes
4MSPS x 1 chan
MCLK max = 24MHz MCLK: VSMP ratio is 6:1 MCLK max = 24MHz MCLK: VSMP ratio is 3:1 MCLK max = 24MHz MCLK: VSMP ratio is 2:1 MCLK max = 24MHz MCLK: VSMP ratio is 2n:1, n 4 MCLK max = 24MHz MCLK: VSMP ratio is 2n:1, n 4
SetReg1: 07(hex)
SetReg1: 05(hex)
3
Fast Monochrome/ Colour Line-by-Line
Yes
8MSPS x 1 chan
Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible
Identical to mode 2
4
Maximum speed Monochrome/ Colour Line-by-Line Slow Colour Pixel-by-Pixel
No
12MSPS x 1 chan
Identical to mode 2
SetReg1: 45(hex)
5
Yes
3MSPS x 3 chans
Identical to mode 1
Identical to mode 1
Identical to mode 1
6
Slow Monochrome/ Colour Line-by-Line
Yes
3MSPS x 1 chan
Identical to mode 2
Identical to mode 2
Identical to mode 2
Table 5 WM8195 Operating Modes Notes: 1. 2. In Monochrome mode, Setup Register 3 bits 7:6 determine which input is to be sampled. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode.
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WM8195
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 14-bit parallel format output and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data.
16.5 MCLK PERIODS
MCLK VSMP
INPUT VIDEO OP[13:0] (DEL = 00) OP[13:0] (DEL = 01)
R G B R G B R G B R G B R G B
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
OP[13:0] (DEL = 10)
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
OP[13:0] (DEL = 11)
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
Figure 21 Mode 1 Operation
Figure 22 Mode 2 Operation
Figure 23 Mode 3 Operation
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Figure 24 Mode 4 Operation
16.5 MCLK PERIODS
MCLK VSMP
INPUT VIDEO OP[13:0] (DEL = 00) OP[13:0] (DEL = 01) OP[13:0] (DEL = 10) OP[13:0] (DEL = 11)
X R G B X R G B X R G B X R G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
Figure 25 Mode 5 Operation (MCLK:VSMP Ratio = 8:1)
Figure 26 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)
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WM8195
DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the WM8195. The register map is programmed by writing the required codes to the appropriate addresses via the serial or parallel interface.
ADDRESS 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 100000 100001 100010 100011 101000 101001 101010 101011 Setup Reg 1 Setup Reg 2 Setup Reg 3 Software Reset Auto-cycle Reset Setup Reg 4 Revision Number Setup Reg 5 Setup Reg 6 Reserved Reserved Reserved DAC Value (Red) DAC Value (Green) DAC Value (Blue) DAC Value (RGB) PGA Gain (Red) PGA Gain (Green) PGA Gain (Blue) PGA Gain (RGB) DESCRIPTION DEF (hex) 03 20 1F 00 00 00 41 00 00 00 00 00 80 80 80 80 00 00 00 00 RW RW RW W W RW R RW RW RW RW RW RW RW RW W RW RW RW W 0 0 0 0 0 DAC[7] DAC[7] DAC[7] DAC[7] PGA[7] PGA[7] PGA[7] PGA[7] 0 0 0 0 0 DAC[6] DAC[6] DAC[6] DAC[6] PGA[6] PGA[6] PGA[6] PGA[6] 0 0 0 0 0 DAC[5] DAC[5] DAC[5] DAC[5] PGA[5] PGA[5] PGA[5] PGA[5] POSNNEG 0 0 0 0 DAC[4] DAC[4] DAC[4] DAC[4] PGA[4] PGA[4] PGA[4] PGA[4] VDEL[2] SELDIS[3] 0 0 0 DAC[3] DAC[3] DAC[3] DAC[3] PGA[3] PGA[3] PGA[3] PGA[3] VDEL[1] SELDIS[2] 0 0 0 DAC[2] DAC[2] DAC[2] DAC[2] PGA[2] PGA[2] PGA[2] PGA[2] VDEL[0] SELDIS[1] 0 0 0 DAC[1] DAC[1] DAC[1] DAC[1] PGA[1] PGA[1] PGA[1] PGA[1] VSMPDET SELDIS[0] 0 0 0 DAC[0] DAC[0] DAC[0] DAC[0] PGA[0] PGA[0] PGA[0] PGA[0] FM[1] FM[0] INTM[1] INTM[0] RLCINT FME ACYCNRLC LINEBYLINE DEL[1] CHAN[1] RW b7 b6 MODE4 DEL[0] CHAN[0] b5 PGAFS[1] RLCDACRNG CDSREF [1] b4 PGAFS[0] 0 CDSREF [0] BIT b3 SELPD VRLCEXT RLCV[3] b2 MONO INVOP RLCV[2] b1 CDS MUXOP[1] RLCV[1] b0 EN MUXOP[0] RLCV[0]
Table 6 Register Map
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REGISTER MAP DESCRIPTION
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The following table describes the function of each of the control bits shown in Table 7. REGISTER Setup Register 1 BIT NO 0 BIT NAME(S) EN DEFAULT 1 DESCRIPTION When SELPD = 1 this bit has no effect. When SELPD = 0 this bit controls the global power down: 0 = complete power down, 1 = fully active. Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Mono/colour select: 0 = colour, 1 = monochrome operation. Selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by SELDIS[3:0]). Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 6 Setup Register 2 1:0 MODE4 MUXOP[1:0] 0 00 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video)
1 2 3 5:4
CDS MONO SELPD PGAFS[1:0]
1 0 0 00
Required when operating in MODE4: 0 = other modes, 1 = MODE4. Determines the output data format. 00 = 14-bit parallel 01 = 8-bit multiplexed (8+6 bits) 10 = 7-bit multiplexed mode (7+7 bits) 11 = 4-bit multiplexed mode (4+4+4+2 bits)
2
INVOP
0
Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative going video gives positive going output data. When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods
3 5
VRLCEXT RLCDACRNG
0 1
7:6
DEL[1:0]
00
Setup Register 3
3:0
RLCV[3:0]
1111
Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods 10 = Blue channel select 11 = Reserved
5:4
CDSREF[1:0]
01
7:6
CHAN[1:0]
00
Monochrome mode channel select. 00 = Red channel select 01 = Green channel select
Software Reset Auto-cycle Reset
Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP. This function is only required when LINEBYLINE = 1.
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Production Data REGISTER Setup Register 4 BIT NO 0 BIT NAME(S) LINEBYLINE DEFAULT 0 DESCRIPTION
WM8195
Selects line by line operation 0 = normal operation, 1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input pin and the input multiplexer and offset/gain register controls. 0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input and gain/offset multiplexers, 1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin. See Table 4, Colour Selection Description in Line-by-Line Mode for colour selection mode details. When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset level clamping. The RLCINT bit may be used instead. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit controls the input force mux mode: 0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected by FM[1:0] separately from gain and offset multiplexers. See Table 4 for details. When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine whether Reset Level Clamping is used. 0 = RLC disabled, 1 = RLC enabled. Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 4 for details. Colour selection bits used in input force mux modes. 00 = RINP, 01 = GINP, 10 = BINP and 11 = Reserved. See Table 4 for details. 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 19, Internal VSMP Pulses Generated for details. When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 19 for further details. Selective power disable register - activated when SELPD = 1. Each bit disables respective cell when 1, enabled when 0. SELDIS[0] = Red CDS, PGA SELDIS[1] = Green CDS, PGA SELDIS[2] = Blue CDS, PGA SELDIS[3] = ADC
1
ACYCNRLC
0
2
FME
0
3
RLCINT
0
5:4
INTM[1:0]
00
7:6
FM[1:0]
00
Setup Register 5
0
VSMPDET
0
3:1
VDEL[2:0]
000
4
POSNNEG
0
Setup Register 6
3:0
SELDIS[3:0]
0000
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WM8195
REGISTER Offset DAC (Red) Offset DAC (Green) Offset DAC (Blue) Offset DAC (RGB) PGA gain (Red) PGA gain (Green) PGA gain (Blue) PGA gain (RGB) BIT NO 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 BIT NAME(S) DAC[7:0] DAC[7:0] DAC[7:0] DAC[7:0] PGA[7:0] PGA[7:0] PGA[7:0] PGA[7:0] DEFAULT 0 0 0 0 0 0 0 0 Red channel offset DAC value. Green channel offset DAC value Blue channel offset DAC value DESCRIPTION
Production Data
A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = 208/(283-PGA[7:0]) Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = 208/(283-PGA[7:0]) Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = 208/(283-PGA[7:0]) A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value
Table 7 Register Control Bits
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Production Data
WM8195
RECOMMENDED EXTERNAL COMPONENTS
DVDD1 DVDD2, 3 10 24 35 C1 C2 C3 18 25 30 36 40
DVDD1 DVDD2 DVDD3
DGND1 DGND2 DGND3 DGND4 DGND5
DGND AVDD 43 C4 44 AVDD1
AGND1 AGND2 AGND3 AVDD2 AGND4 AGND5 AGND 8 RINP GINP BINP VRT VRX 2 C10 VRLC/VBIAS VRB AGND6
3 5 7 9 45 46
Video Inputs
AGND 48 1 47 C7 C8 C9 C5 C6
6 4
AGND
WM8195
AGND 17 15 39 38 37 34 33 32 31 29 28 27 26 23 22 21 DVDD1 + C11 DVDD2, 3 + C12 AVDD1, 2 + C13 MCLK VSMP OP[13]/SDO OP[12] OP[11] 12 14 13 SEN/STB SCK/RNW SDI/DNA RLC/ACYC NRESET OP[10] OP[9] OP[8] OP[7] OP[6] OP[5] 11 OEB OP[4] OP[3] OP[2] OP[1] OP[0]
Timing Signals
Interface Controls
16 42
Output Data Bus
AGND
NOTES: 1. C1-10 should be fitted as close to WM8195 as possible. 2. AGND1-6 and DGND1-5 should be connected as close to WM8195 as possible. 3. DVDD1-3 should be connected as close to WM8195 as possible.
Figure 27 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 SUGGESTED VALUE 100nF 100nF 100nF 100nF 10nF 1F 100nF 100nF 100nF 100nF 1F 1F 1F DESCRIPTION De-coupling for DVDD1. De-coupling for DVDD2. De-coupling for DVDD3. De-coupling for AVDD1 and AVDD2. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD1. Reservoir capacitor for DVDD2 and DVDD3. Reservoir capacitor for AVDD1 and AVDD2.
Table 8 External Components Descriptions
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WM8195 PACKAGE DIMENSIONS
FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C
Production Data
b
e
25
36
37
24
E1
E
48
13
1
12
c
D1 D
L
A A2
A1 -Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 3.5 7 0 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Production Data
WM8195
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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PD Rev 4.1 July 2005 33

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